A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD

On Compact Test Sets for Multiple Stuck-At Faults for Large Circuits p. 20 Identification of Feedback Bridging Faults with Oscillation p. 25 Delay Fault and Memory Test Defining SRAM Resistive Defects and Their Simulation Stimuli p. 33 Vector-Based Functional Fault Models for Delay Faults p. 41 Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers p. 47 March Tests for Word-Oriented Two-Port Memories p. 53 ATPG Related Approaches II An Evaluation of Test Generation Algorithms for Combinational Circuits p. 63 Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits p. 70